1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a flash write function such as a VRAM (VIDEO Random Access Memory) for storing image data.
2. Description of the Related Art
FIG. 1 shows part of a memory cell array constituting a core of the conventional VRAM, where only two columns are shown for the sake of simplification of description.
In FIG. 1, MC is a dynamic memory cell, WL is a word line, where two MCs and one WL are illustrated by way of example. Paired complementary bit lines (BLi, /BLi) are connected to a pair of data lines of plural paired data lines (DQRi, /DQRi) through paired bit line transfer gates (Q1, Q2) and paired column selecting transfer gates (CS, CS), respectively.
FIG. 2 exemplifies how main signals vary with time to describe an example of the circuit operation of FIG. 1.
Now, an example of the circuit operation shown in FIG. 1 will be briefly described, with reference to FIG. 2.
First, when /RAS (row address strobe) signal is at "H" level (i.e. in a non-active state), the equalizing signal EQL turns into "H" level (i.e. in an active state), so that the equalizing circuit 10 turns into an ON state. The first paired bit lines on the side of the P-channel sense amplifier are thereby pre-charged and equalized to have the bit line potential VBL through the equalizing circuit 10. The second paired bit lines on the side of the N-channel sense amplifier are pre-charged with the bit line potential VBL through the paired bit line transfer gates (Q1, Q2).
When /RAS signal is at "L" level (i.e. in an active state) and a row address is fetched, the EQL signal turns into "L" level (i.e. in a non-active state), so that the equalizing circuit 10 turns into an OFF state. Bit lines are thereby disconnected from the power source potential VCC, the ground potential VSS and the bit line potential VBL. If a word line which corresponds to the fetched row address is selected, memory cell data on the selected row is read on the bit lines. In addition, when the sense amplifier 12 operates, the potential difference between the paired bit lines is amplified. When the sense amplifier 11 operates, the potential of the paired bit lines is determined.
When /RAS signal is back to "H" level, the EQL is back to "H" level, too, so that the equalizing circuit 10 turns into an ON state. Whereby, the first paired bit lines are again pre-charge equalized to have the bit line potential VBL through the equalizing circuit 10. The paired second bit lines are pre-charged with the bit line potential VBL through the paired bit line transfer gates (Q1, Q2).
The above-described operation requires the bit lines to be sufficiently equalized before the sense amplifier 12 starts operating. That is, the paired bit lines need to be pre-charged with the bit line potential VBL through the paired bit line transfer gates (Q1, Q2).
In this regard, in a region where the power source potential VCC is high, e.g. 5 V, the capacity of the bit line transfer gate transistors (Q1, Q2) is sufficient and the threshold voltage Vth is relatively lower than the power source potential VCC. As a result, the second paired bit lines are sufficiently pre-charged with the bit line potential VBL in a short period of time.
Conversely, however,in a range where the power source potential VCC is low, the capacity of the bit line transfer gate transistors (Q1, Q2) is not sufficient and the threshold voltage Vth is not small enough to be negligible compared with the power source potential VCC. As a result, it becomes difficult that the second paired bit lines are sufficiently pre-charged with the bit line potential VBL in a short period of time. Unless the second paired bit lines are sufficiently pre-charged as mentioned above, the margin of a sense operation in the next cycle is greatly decreased. This might cause erroneous sensing of data read from the memory cells.
The first conceivable measure to solve the above problem is to prevent a decrease in potential by the threshold voltage Vth of the transistors, by removing the bit line transfer gate transistors (Q1, Q2) and to thereby sufficiently pre-charge the second paired bit lines.
Nonetheless, if the bit line transfer gate transistors (Q1, Q2) are removed, an apparent bit line capacity at the time of the initial sense operation of the sense amplifier 12 becomes large to such an extent as to make a high-speed, reliable sense operation difficult.
Furthermore, the second measure is to increase the gate potential of the bit line transfer gate transistors (Q1, Q2) to a potential greater than VCC+Vth only for a predetermined period of time, e.g. while the /RAS signal is at "H" level. This allows the transistors (Q1, Q2) to operate in a triode region to compensate for reduced potential caused by the threshold voltage Vth of the transistors (Q1, Q2), thereby pre-charging the second paired bit lines sufficiently.
If trying to increase the gate potential of the whole bit line transfer gate transistors (Q1, Q2) in the memory cells to be greater than VCC+Vth in a short period of time to activate them, a voltage booster circuit employing a large-capacity, large-size capacitor is needed. Besides, since the VRAM usually operates in an asynchronous manner, there is a strong possibility that the voltage booster circuit malfunctions by the operation of the serial access memory (SAM) port, in particular, by the power source noise which occurs at a time when data is output.
As described above, the conventional semiconductor memory device has had such disadvantages that it is difficult to sufficiently pre-charge bit lines, in a range where the power source potential is low, during a short period of time and that the margin of a sense operation is greatly decreased with the result that erroneous data is likely to be sensed.